04/05/2019
Position Summary:
The Photonics Layout Engineer will be responsible for drawing test structures, devices and full mask layers, in compliance with the given design, process and recommended design rules, while implementing the needed tools to guarantee low error rate, standardized procedures and communication across teams.
Requirements:
• 5+ years experience as a layout designer with the list of skills below
• Some experience writing skill code C++ and ability to learn more
• Experience with L-Edit layout tools and Physical Verification tools
• Ability to learn tools: Phoenix OptoDesigner/OptSim Circuit
• Experience with PDK environments
• Experience with modeling & characterization
• Responsible for the drawing and delivering of files in GDS or other format representing Si-photonic devices
• Develop a building block library based on process flow documentation and design rules
• Develop a Design Rule Check (DRC) routine
• Establish, document, and update design rules for the used processes, and collect process limitations and tolerances, process flow documentation, and related IP
• Standardize and write guidelines for layout scripting
• Implement revision control standards and documentation for layout changes, reviews and approvals
• Be responsible for developing and drawing test structures to monitor and characterize critical device features and process tolerances
• Ensure data, layout and document sharing across locations and teams, working closely with the design team to feedback process capabilities into the design, or explore further processes per designers' request
• Analyze process data, measurement results for developing design rules or feedback process capabilities
