07/10/2024
[Share Job] SOC Engineering, Senior Engineer
from Synopsys:
Mid level, 2YoE ++, HCMC
If you’re ready to excel, innovate, and pursue a passion in ASIC Design Verification for IP, Subsystem or SoC, we’d like to welcome you to our newly created Subsystem Verification Team in Ho Chi Minh city, Vietnam. We are looking for Design Verification talents of various levels: Design Verification Engineers, Leads and Managers. With your expertise, together with the industry most talented professionals in the team, empowered by Synopsys EDA ecosystem, you are fueling the new era of Era of Pervasive Intelligence by offering high-speed silicon-proven interface IP solutions in the latest process technology for the most cutting-edge industry vertical including Artificial intelligence, Autonomous Vehicles, High-Performance Compute, Cloud, 5G Mobile and the IoT etc. IPs and subsystems you make will be integrated into tens of millions of SoCs that are used by billions of people.
You will be joining a true global team that has personality, enthusiasm and a fun culture with diversity. You will have all the support you need to grow and develop with us. No matter where you are in your career, the experience and expertise you grow here will put you miles ahead in the career advancement and open the path to all possibilities.
Responsibilities:
Define verification plans and build verification environments for block/sub-system level designs using Verilog, System Verilog and UVM.
Write test cases, checkers, and coverage that implement the verification test plan.
Apply advanced verification techniques like constrained random generation, functional coverage, assertions, and formal verification.
Work closely with RTL designers and other parts of our global verification team to debug failures.
Qualifications:
Bachelor or Master degree in EE or CS.
2+ years of experience in design verification in the industry.
Knowledge of one or more protocols such as AMBA, PCI-Express, CXL, UCIe, Ethernet, HBM, DDR…
Knowledge of industry-standard simulators, revision control systems, and regression systems.
Experience of RTL verification using coverage driven verification techniques
Experience in developing System Verilog, UVM or similar HDL based test environments.
Programming skills such as HDL, Verilog, System Verilog, C, Perl, Python.
Good analytical, oral, and written communication skills.
Self-motivated, proactive team player.
Synopsys delivers the most trusted and comprehensive silicon to systems design solutions, accelerating technology innovation. We partner closely with our customers to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Companies trust Synopsys to pioneer new technologies to help them get to market faster without compromise.